The core board is similar in function to an XK-1, with the addition of the the PCIe edge connectors to replace the XK-1 IDC headers. This provides for a good deal more IO connectivity at the expense of a larger PCB.
The port connections to the connectors are chosen to satisfy the following constraints:
- Two full 5b xlinks must be available on slot number 0 enabling multiple core boards to be chained together with reasonable inter-chip link bandwidth.
- The JTAG signals and the debug pin must be available on slot number 0 enabling multiple core boards to be chained together for debug.
- Slot number 0 must have at least 4 1b ports on it to enable basic functions to fit in slot 0.
- For higher speed parallel interfaces like ULPI, Transport stream and SDRAM, 1 GND is required for every 4 or 5 signal pins. Note that they probably also need to spaced more evenly but the assignment of functions to pins above can be altered during detailed design as long as the connector still has all the connections listed above.
The slots also export the core board reset signal and the core board reference clock so that slicecards can make use of these functions to avoid component duplication where possible.
Each core board has a 5V power jack. 5V and 3V3 suuplies are be generated from DC-DCs from this main supply and then distributed to all slice connectors. Slices needing core supplies below 3V3 should generate them themselves from the 5V supply to the slice. The core board will generate 1V for the XS1-L.
Slices will have a power budget of approximately 2W each. Each core exports its IO to slice cards via two 36-position PCIe connectors as shown below. Note that the connectors each have two sides (A, corresponding to the teeth on the top of the slice PCB and B, connecting to teeth on the bottom side of the slice PCB).
The connectors are named <slot>_<xcore_number>_<connector_number>.
Standard XMOS debug functionality is provided via a normal XTAG2 which connects to the set of PCIe teeth labeled as ‘Plug_00’ in the preceeding diagram via a simple conversion connector (supplied with the coard board) which maps the XTAG2 XSYS header to the plug_00 teeth.
Note that connectors 0 and 1 are compatible in terms of port connectivity, in that 0 is a subset of 1 in terms of ports. This means that any slice card which is compatible with 0, would also work when connected via 1. Therefore slice cards which work via connector 0 are the most versatile, but slices needing more than 4 1b ports can be designed to fit only in COnnector number 1.
Slices with even larger IO requirements can use both connectors at once in which case it will end up using all the IO of one core and have the full cmoplement of ports available for the slicecard.
P8D[4:7] is not bonded out on the secondary core of an L2. Slices should avoid where possible using 8D[4:7] and 8B[4:7]. Where this is not possible, such slices will not be compatible with slot 1_1.
CLK is a fixed 25 MHz reference clock generated by an crystal oscillator on the core board which is the default reference clock for the XMOS chip and is distributed to all slicecards via the CLK pin. Slices can use this clock or generate their own.
Both slots have 5V, 3V3, and GND. 5V, 3V3 and GND.
Connector 0 is special because it brings out the JTAG signals and because two 5-wire xlinks overlay the ports selected for inclusion on connector 0, this means that connector 0 can be used for connecting multiple core boards together. A jumper (or similar) willbe present to enable TDI and TDO to be shorted when no card is plugged in. If a connector does not bring out JTAG, all parenthesised pins should be NC.
All core boards export the IO from xcore0 to both connector 0 (as above) but also to an adjacent set of connector compatible teeth marked ‘chain’ in the diagram above. An example of an L2 core board as an xlink boot master to a connected L1 core board is shown below. Two L1 or twi L2 boards could be similarly connected.
Lastly, provision will be made to pass the 12V supply from the primary board to a suitable connection on the secondary board so that two bricks are not required.